Magnetoresistive random-access memory (“MRAM”) is a non-volatile memory technology that stores data through magnetic storage elements. These magnetic storage elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. In general, one of the plates has its magnetization pinned (i.e., a “reference layer”), meaning that this layer has a higher coercivity than the other layer and requires a larger magnetic field or spin-polarized current to change the orientation of its magnetization. The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
MRAM devices store information by changing the orientation of the magnetization of the free layer. In particular, based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a “1” or a “0” can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers. The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a “1” and a “0.” One important feature of MRAM devices is that they are generally considered as non-volatile memory devices, since they maintain the information even when the power is off. The two plates can be sub-micron in lateral size and the magnetization direction can still be stable with respect to thermal fluctuations.
MRAM devices are considered as the next generation structures for a wide range of memory applications. MRAM products based on spin torque transfer switching are already making its way into large data storage devices. Spin transfer torque magnetic random access memory (“STT-MRAM”) has an inherently stochastic write mechanism, wherein bits have certain probability of write failure on any given write cycle. The write failures are most generally random, and have a characteristic failure rate. A high WER may make the memory unreliable.
In memory devices, error correction is commonly used to achieve reliable write performance and to reduce post-ECC failure rates to acceptable levels. Error correction coding requires extra memory in the array to store parity bits. The requirement for additional memory may cause a significant increase in memory array size, and/or reduction of memory capacity for the devices having an inherently high WER such as STT-MRAM, either of which are highly undesirable. Further the ECC encoder/decoder circuits may be complex, large, slow, and use a great deal of power when active.
Thus, there is a need for a technology that can be used with STT-MRAM to ensure reliable write performance with low ECC failure rates, even with devices that have inherently high WER.